System Overview


The Multichannel Analyzer (MCA) consists of a detector front-end and a signal-processing and display device. This device is what our team is responsible for.

The X-ray detection front-end was given to us by GSFC. This consists of a commerical detector, preamplifier, and shaping amplifier that take X-ray photons and convert them into a voltage pulse. The front-end provides a pulse such that the peak voltage is directly proportional to the photon energy.

Our team is responsible for interpreting and displaying the front-end's voltage pulses. The diagram below illustrates how we do this.

Block Diagram

Block diagram
Figure 1: The diagram shows major components of our MCA. The incoming signal is the voltage output of the shaping amplifier. Knobs specify values that the user will be able to control.

A signal comes in with voltage values from 0-10 V. It is fed into two separate locations.

1) The spectral channel, consisting of the Peak-and-Hold and the ADC, acquires the peak height of the voltage pulses. The signal goes into the peak-and-hold circuit. This circuit outputs a voltage that is equal to the highest voltage level that has come in. When a pulse arrives, the voltage output increases until the pulse reaches maximum height. The peak-and-hold retains this voltage value. When prompted, the analog-to-digital converter (ADC) will convert the voltage into a 10-bit signal that can be read by the PIC. Once the ADC has finished, the PIC will reset the peak-and-hold circuit. By restoring the circuit to its baseline, the PIC makes the peak-and-hold ready for the next pulse.

2) The fast channel, consisting of the comparator and flip-flop, counts the number of pulses and helps determine when to sample from the peak-and-hold. The comparator outputs a high voltage if the pulse signal is above threshold, screening out low-voltage noise. The comparator's output is hooked up to the PIC's Timer0. Timer0 increments on the comparator's rising edge, making it a reliable hardware counter independent of clock speed.

The comparator output is also held by a memory element, a JK flip-flop or an SR latch. The PIC waits a short time interval. This time is just a little longer than the rise-time of the voltage pulse plus the response time of the peak-and-hold circuit. After waiting, the PIC enables the ADC. The PIC waits another time interval until the ADC sampling is finished. Now, the PIC resets the peak-and-hold as well as the memory element. Note that the memory element prevents the system from paralyzing: in order for a new sampling cycle to start, the old cycle has to end first.

Timing Diagram

Our MCA performs event detection using the timing channel, as described above. The hardware and firmware detects events and chooses when to sample from the peak-and-hold circuit. The timing diagram gives a visual representation of how this happens.

Timing diagram
Figure 2: The blue lines represent signals. The events of the entire timing diagram take place within ~8 microseconds.

Additional Detail

For more detail on the MCA design, please go to the pages on 'Firmware' and 'Software'.