Analog Circuitry

Introduction

On the analog side of the device, there are several tasks to convert a signal into a format that can be sent to a computer. First, we apply a gain to our signal. Then, we differentiate the signal so that we can detect peaks. Once we do detect a peak, we do two things. First, we increment a counter so that we can keep track of the number of pulses. Second, we convert the analog signal to a digital value so that we know how high the peak was. This information is then read by a PIC, which then sends it in a constant stream to the computer.

Small Analog Circuit
MCA Circuit Schematic
(click to download full-size version)

Circuit Operation

Please refer to the accompanying ExpressPCB schematic while reading the following explanation. A downloadable image is also available at right.

Peak and hold

The heart of the pulse height detector is a peak and hold circuit consisting of a diode and a capacitor. The capacitor will only charge if current flows into it. Current will only flow into the capacitor if there is a forward voltage drop across the diode. This only occurs if the voltage value of the input signal is higher than the value stored in the capacitor. Thus, the capacitor will charge up with the input until it reaches its peak, at which point it retains its value until cleared. To obtain a fast rise time with a 50 ohm impedance input signal, the capacitance is necessarily very small (10 pf). Since any flow of current out of the capacitor would drain it very quickly, as it has such a small capacitance value, a FET opamp is used as a buffer. Similarly, the junction capacitance of the diode means that the capacitor forms part of a capacitave divider. If unaccounted for, this causes some multiple of the input signal to ride on top of the stored maximum height, even when it is less than the maximum recorded peak. This can be rather severe, as the BAT41 has a junction capacitance of 1 pF. To ensure that the stored value does not vary as we measure it, we decouple the input into the diode-capacitor from the input, letting it float down to a constant value lower than any of our input signals (-12 V). However, this has the effect of lowering the stored value (as the capacitive divider still exists - it is just constant). To avoid this, when high rise time (and thus low capacitance) is not a concern, a 100 pF capacitor can be placed in parallel with the 10 pF capacitor, to form a 110 pF capacitor which is relatively unaffected by this coupling, by toggling a switch that is affixed to the circuit board near the place marked P H S (Pole (the center of the switch), High speed, Low speed). The ADC can only accept signals of up to 5 volts, so a circuit limiting diode is placed after the buffer to ensure that the ADC is not damaged. However, the circuit is not designed to be used with input above 5 volts, as the diode could possibly be overpowered by the opamp (an area of improvement).

Fast counter

The Input signal is also differentiated by a passive RC circuit with a diode to shorten the negative swing of the differentiator output as the pulse subsides. This output is then fed into a comparator that outputs logic high whenever its input is higher than a threshold voltage set by the user in software. If this is the case, we are said to have encountered a countable pulse. This pulse is then fed into a logic AND with a coincidence/anticoincedence pulse. This pulse must also be true for the event to be counted. in solo mode this input to this AND is always set to true. The switch which sets this is ideally a single-pole triple-throw switch connected near the P A C S (Pole Anti Co Solo) marking on the board. Please see the assembly section for details, as this marking needs to be revised on the current revision of the board. The resulting pulse is fed into a 74HC4040 counter chip which increments an internal 12 bit binary counter on each pulse. The value of the register in the counter is read out by the PIC from time to time and its value reset. The pulse is also inverted and fed into a 74HC74 chip (a D type latch), which detects the falling edge of our pulse. When this falling edge occurs, our pulse has reached its maximum value. 74HC74 chip, if it was outputting zero before, switches to outputting true. This decouples the input from the peak and hold (see above), and alerts the PIC that we have stored a pulse height that needs to be read off using the ADC.

Reseting the system

When this pulse height has been read, the PIC sends a logic pulse to both the 74HC74 and the DG212 Analog switch. The switch resets the value of the peak and hold by shorting the capacitor to -12V, and the 74HC74 resets its internal stored bit to zero, so that it is ready to latch the next countable pulse. As this occurs, the 74HC74 also re-couples the input with the peak and hold.

Circuit Board

Schematic

Click here to download an image of the circuit schematic. Click here to download a copy of the circuit schematic (ExpressSCH file format).

PCB Layout

Click here to download an image of the printed circuit board we designed. Click here to download a copy of the PCB design (ExpressPCB file format).

Bill of Materials

To quantify one of our primary objectives - meeting cost requirements - we generated a bill of materials for all the parts included in our prototype design. Click here to view the itemized list.

Parts